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Error-Check for Drum Compare Circuitry

IP.com Disclosure Number: IPCOM000098769D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

D'Antonio, RA: AUTHOR

Abstract

The purpose of the apparatus is to error check the operation of the circuitry used for comparing corresponding flip flop pairs, such as 11 and 21, of drum compare registers 10 and 20. Successive sampling pulses from conductors P1 and P2 are applied via OR circuit 35 to each status comparing matrix, such as gates 31-34, individual to each pair of register flip flops. In order to insure a complete comparison check and to thereafter restore the register flip flops to original condition, the P1 and P2 pulses pass through delay lines 37 and 38, respectively, and OR circuit 36 to complement inputs of all register flip flops. Pulses passed by delay line 38 also reset flip flop 40 to its 0 state.

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Error-Check for Drum Compare Circuitry

The purpose of the apparatus is to error check the operation of the circuitry used for comparing corresponding flip flop pairs, such as 11 and 21, of drum compare registers 10 and 20. Successive sampling pulses from conductors P1 and P2 are applied via OR circuit 35 to each status comparing matrix, such as gates 31-34, individual to each pair of register flip flops. In order to insure a complete comparison check and to thereafter restore the register flip flops to original condition, the P1 and P2 pulses pass through delay lines 37 and 38, respectively, and OR circuit 36 to complement inputs of all register flip flops. Pulses passed by delay line 38 also reset flip flop 40 to its 0 state.

Normally, each matrix passes either no pulse (for a compare situation) or a pair of successive pulses (for a no compare situation). Matrix output pulses pass through OR circuit 41 to the NO COMPARE output and the complement input of flip flop 40. Such pairs of pulses place flip flop 40 in its 0 state, and consequently block the passage of any P2 pulse (via delay line 38) through gate 39. Failure of any matrix gate is indicated at some time by passage of a single pulse to the complement input of flip flop 40. At such a time, gate 39 is enabled and passes the aforementioned P2 pulse to the ERROR output.

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