Browse Prior Art Database

Stepping

IP.com Disclosure Number: IPCOM000098779D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Hine, SR: AUTHOR

Abstract

A counter which has binary coded decimal triggers T1-T2-T4-T8 and associated logic, but which operates in a modified B.C.D. code (upper circuit and Table A), provides a redundancy indication for checking of setting and stepping with the addition of only one check trigger TC.

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Stepping

A counter which has binary coded decimal triggers T1-T2-T4-T8 and associated logic, but which operates in a modified B.C.D. code (upper circuit and Table A), provides a redundancy indication for checking of setting and stepping with the addition of only one check trigger TC.

Another counter which has triggers T1-T2-T4-T8 and which operates in a conventional B.C.D. code (lower circuit and Table B) also provides a redundancy indication for checking of setting and stepping with the addition of a redundancy trigger TR and a check trigger TC.

The differences between the basic 1-2-4-8 bit configurations of the modified B.C.D. version and the conventional B.C.D. 1-2-4-8 bit configurations are indicated in Table A by Small x's-placed in appropriate squares. For example, if a 5 is represented. T(8) is ON as well as the conventional T(4) and T(1).

Each counter shown is capable of providing an even redundancy indication for numerical data transferred in in parallel from an outside source, such as another counter. Each counter is also capable of an even redundancy indication during counting operations. A check for even redundancy of a particular counter may be made by directing the status lines of each trigger position in that counter to a logical network (not shown), which would give an error indication if redundancy was not proper, either on Transfer In or during Stepping operations.

Transfer In or Stepping operations occur under control of signals which assume an up level 1 or a down level 0 in a binary fashio...