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Trigger Register

IP.com Disclosure Number: IPCOM000098792D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Steckenrider, RN: AUTHOR

Abstract

The drawing shows a voltage mode trigger register which permits a simultaneous application of a set and reset pulse. The usual additional time allowance for the reset operation is eliminated. The set pulse always overcomes the effect of the reset pulse to control the final state of the trigger.

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Trigger Register

The drawing shows a voltage mode trigger register which permits a simultaneous application of a set and reset pulse. The usual additional time allowance for the reset operation is eliminated. The set pulse always overcomes the effect of the reset pulse to control the final state of the trigger.

The trigger register comprises the usual pair of cross coupled transistors 1 and 2. Transistor 1 is cross coupled through an associated transistor emitter follower 3 and capacitor resistor network 4 to transistor 2. Transistor 2 is similarly cross coupled through an associated transistor emitter follower 5 and capacitor resistor network 6 to transistor 1. In the ON state of the register, transistor 2 is in saturation. In the OFF state, transistor 1 is in saturation. Terminals 7 and 8 provide output indications from the ON and OFF sides, respectively, of the trigger.

With the trigger ON, the base and collector of the saturated transistor 2 are at approximately ground potential. The base is linked to one electrode of a gate diode 9. The collector ground potential is effective through the emitter follower action of transistor 5, terminal 7, conductor 10 and resistors 11 and 12 to hold the associated electrode of diode 9 at ground potential. With the diode 9 thus conditioned, the application of a positive going reset pulse to terminal 13 is transmitted through a capacitor 14 to diode 9 and is effective through the diode to drive transistor 2 OFF. As transistor 2 goes OFF, the resulting negative shift of its collector is effective through the associated transistor 5 and network 6 to drive transistor 1 into saturation. The effect of the saturation of transistor 1 is fed back through transistor 3 and network 4 to aid in transferring the transistor to the OFF state and maintain it in such state.

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