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Hole Count Verifier

IP.com Disclosure Number: IPCOM000098795D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Droege, FJ: AUTHOR [+3]

Abstract

Circuitry is provided for verifying card reading when the card columns are either blank or contain one, two or three holes. The card is read at two successive stations and the number of holes read in each column at the two stations is compared.

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Hole Count Verifier

Circuitry is provided for verifying card reading when the card columns are either blank or contain one, two or three holes. The card is read at two successive stations and the number of holes read in each column at the two stations is compared.

Card data are read a first time, column by column, at read station 1 and stored in a storage unit 2. Thereafter the data are read out of unit 2 by a driver unit 3 through lines 4, and through.terminal blocks 5 and 6 are fed into a Hole Count Logic unit 7.

The card may be read in any code but is converted to an alphanumeric binary code X, 0, 8, 4, 2, 1. The 4 bit is not determinant of any particular number of holes and therefore is not used in the verifying.

X and 0 (zone) bits are fed to an OR circuit 10. The 8 and 2 bits are fed in parallel to an OR circuit 11 and an AND circuit 12. 1 bits are fed to the OR circuit
11.

An output from OR 10 in response to an X or an O bit is fed to OR 13. One or more 8, 2 or 1 bits effect an output from OR 11 and thus provide an input to OR 13. OR 13 responds to an input from either or both OR 10 and OR 11 and actuates AND 16 to manifest at drivers 17 the sensing of one or two holes. If both 8 and 2 bits are present, indicating three holes (in combination with X or 0), the output of AND 12 actuates AND 14 to inhibit AND 16.

AND 15 is actuated by the combination of an X bit or an 0 bit with one or more of bits 8, 2 and 1 and the output is fed to OR 18 to manifest at driv...