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Core Memory Protective Circuit

IP.com Disclosure Number: IPCOM000098803D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Booth, RR: AUTHOR

Abstract

In a high speed memory too frequent use of the same storage location may cause overheating of the memory cores and consequent deterioration of their storage ability. This circuit monitors the repetition rate of the unipolar word selection drivers for the two dimensional coincident current memory and indicates when a dangerous condition exists.

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Core Memory Protective Circuit

In a high speed memory too frequent use of the same storage location may cause overheating of the memory cores and consequent deterioration of their storage ability. This circuit monitors the repetition rate of the unipolar word selection drivers for the two dimensional coincident current memory and indicates when a dangerous condition exists.

The monitor circuit employs a variation of the bucket and ladle method of counting pulses with magnetic cores. A bucket type core is coupled to each word write drive line and is driven part way up its hysteresis loop each time the associated word storage location is addressed, as shown in the hysteresis diagram at the right. The bucket core is chosen so that a normal memory address pulse, which comprises the ladle, switches only a fraction of its flux. A constant low amplitude bias on the core slowly switches the flux back toward the reset state between drive pulses. Assuming that the drive pulses do not occur too frequently, the bias force maintains the core in the lower portion of the hysteresis loop at all times. An output is induced on the sense line in response to each drive pulse. If, however, a particular storage location is addressed too frequently, the associated monitor core is stepped up its loop to the positive saturation point and subsequent drive pulses switch no flux and produce no sense output. This lack of output is employed to signal a fault condition in which the memory may...