Browse Prior Art Database

Multi Stable Transistor Core Counter

IP.com Disclosure Number: IPCOM000098806D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Kuntzleman, HC: AUTHOR [+2]

Abstract

A magnetic core counter stage is constructed from a core 1 capable of being driven incrementally toward a saturation state by successive input pulses on a line 2, such core preferably having essentially rectangular hysteresis loop characteristics.

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Multi Stable Transistor Core Counter

A magnetic core counter stage is constructed from a core 1 capable of being driven incrementally toward a saturation state by successive input pulses on a line 2, such core preferably having essentially rectangular hysteresis loop characteristics.

A predetermined number of input pulses, for example ten (see right hand figure), through core winding 3, step the core to a slate of saturation. A resistor 4 is adjustable and functions to vary the radix of the counting circuit.

When the core 1 saturates, the voltage across the winding 3 decreases to substantially zero magnitude and the voltage of the input pulse appearing across a resistor 5 is sufficient to render the switching transistor 6 conductive. With the transistor conducting the current flow through the emitter E, collector C, the reset winding 7 and load resistor 8 resets the core 1 to its original state.

During reset, an output voltage pulse is developed across the load resistor 8 which is capacitively coupled to the output terminal 9.

The current flow induced in winding 3 during reset is shorted to ground through diode 10.

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