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Bipolar Analog Digital Conversion Circuit

IP.com Disclosure Number: IPCOM000098818D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Margopoulos, WP: AUTHOR [+2]

Abstract

A circuit for converting a positive or negative analog voltage E(I) ,by successive approximation, to an equivalent digital representation in the register T32-Tn is provided by two comparators C1 and C2, and associated gating. These permit the establishment of an absolute digital value in the register, regardless of the polarity of the applied signal E(I), and eliminate the necessity for complementing the register.

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Bipolar Analog Digital Conversion Circuit

A circuit for converting a positive or negative analog voltage E(I) ,by successive approximation, to an equivalent digital representation in the register T32-Tn is provided by two comparators C1 and C2, and associated gating. These permit the establishment of an absolute digital value in the register, regardless of the polarity of the applied signal E(I), and eliminate the necessity for complementing the register.

The input voltage E(I) is compared with a precision reference voltage E(R) which is established under control of the voltage switches V(S). Each is switched on by a particular one of the triggers T(S), T(32)-T(n) in the register when that trigger is in its 1 or ON state.

Initially the sign trigger T(S) is set to 1 or its Positive indicating state and the triggers T(32)-T(n) are reset to 0 by a reset pulse from terminal R. At this time E(R) is established at a zero level. E(R) is simultaneously applied to C(1) via line 1 and to C2 via line 2. With T(S) is its 1 or Positive state a 1 output is available on line 3 and is applied to AND gate A(1).

As the first step in conversion a determination of the polarity of E(I) is made. If E(I) is positive, T(S) is left in its 1 state, and if E(I) is negative, T(S) is reset. Resetting of T(S) occurs upon the application of a first clock pulse from terminal C and the timing ring, via line 4, to AND gate A(S) only if a 1 output is provided on line 5 from the OR block O(C) as a result of an output from A(1) und...