Browse Prior Art Database

Analog-digital, Digital-Analog Sign Handling

IP.com Disclosure Number: IPCOM000098820D
Original Publication Date: 1959-Dec-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Margopoulos, WP: AUTHOR [+2]

Abstract

Logical circuitry under control of a trigger T(S) is provided in an analog digital conversion network. This circuitry is connected between the digital register represented by the bistable triggers T(32)-T(0) and the trigger controlled voltage switches VS(32)-VS(0) to permit simplified handling of both positive and negative representations.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Analog-digital, Digital-Analog Sign Handling

Logical circuitry under control of a trigger T(S) is provided in an analog digital conversion network. This circuitry is connected between the digital register represented by the bistable triggers T(32)-T(0) and the trigger controlled voltage switches VS(32)-VS(0) to permit simplified handling of both positive and negative representations.

Conversion of an analog potential E(I), held in the amplifier A, is performed by the technique of successive approximation. Initially, all register stages T(32)- T(0) are reset off and the sign trigger T(S) is set to its 1 or plus state by a single reset pulse applied to the terminal 1. With the triggers in this condition, VS(S) is on and a precision zero reference potential E(R) exists at the summing junction J, against which the analog potential E(I) is compared for determination of its polarity. The comparator C provides a binary zero output on line 2 to AND gate A(N), if E(I) is positive with respect to E(R), and a binary one output on line 3 to AND gate A(P), if E(I) is negative with respect to E(R). A(N) and A(P) are gated under control of T(S) via lines 4 and 5, respectively, through the OR block O(C) to line 6. Clock pulses CP from terminal 7 cause stepping of a Timing Ring which provides pulses successively on the lines 8-15.

If E(I) is initially + 5. 0 volts, for example, no output occurs on lines 3 and 6 from C. T(S) remains in its 1 (plus) state, since only the input on line 8 to A(40) is up and A(40) does not provide an out put to reset T(S). In this condition T(S) gates A(P) via line 5 and the gates A(50)-A(56) via line 16. If E(I) is...