Browse Prior Art Database

Memory Address Checking

IP.com Disclosure Number: IPCOM000098833D
Original Publication Date: 1958-Jun-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Bashe, CJ: AUTHOR

Abstract

This device relates to memory address checking. The address part of an instruction is provided with a parity bit of its own so that the total count of 1's in the address is even (or odd). Thus, address 26 would be binary coded 0011010 requiring a 1 bit for even parity while address 27 would be binary coded 0011011 requiring a 0 bit for even parity. Since the parity bit is always the same for a given memory address, regardless of the data word stored at that address, the parity bit associated therewith may be permanently stored in an extra plane so arranged that cores appear only in locations whose address requires a 1 bit for the parity bit.

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Memory Address Checking

This device relates to memory address checking. The address part of an instruction is provided with a parity bit of its own so that the total count of 1's in the address is even (or odd). Thus, address 26 would be binary coded 0011010 requiring a 1 bit for even parity while address 27 would be binary coded 0011011 requiring a 0 bit for even parity. Since the parity bit is always the same for a given memory address, regardless of the data word stored at that address, the parity bit associated therewith may be permanently stored in an extra plane so arranged that cores appear only in locations whose address requires a 1 bit for the parity bit.

The address part of the instruction including its parity bit is stored in an address register, after which the data word located at the designated address, together with the permanently stored parity bit, is read out of memory. The permanently stored parity bit is then compared with the parity bit of the designated address. If they are equal, it indicates that the data word was read out of the proper location. If they are not, an alarm is signalled. This method of checking address selection may be applied to any addressable memory whether it be magnetic core, cathode ray, superconductive, ferroelectric, etc.

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