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Memory Address Checking

IP.com Disclosure Number: IPCOM000098866D
Original Publication Date: 1958-Aug-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Constantine, G: AUTHOR

Abstract

This is a system for memory address checking. The left-hand diagram shows a segmented memory with a pair of matrix selection switches providing the X and Y selection for each segment. Each matrix switch has an address encoder provided, one of which is shown in the right hand diagram. In the address encoder, a magnetic core is provided for each output and a group of seven sense wires are wound through the cores to identify the selected X or Y wire from the selected matrix switch. Sense wires ABC identify the selected matrix switch while sense wires 1, 2, 4, 8 identify the selected X or Y wire therefrom. The encoders associated with MS-7, MS-6, MS-5 etc. have the sense wires ABC, BC, AC etc., respectively, passing through all of the cores of the associated encoder.

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Memory Address Checking

This is a system for memory address checking. The left-hand diagram shows a segmented memory with a pair of matrix selection switches providing the X and Y selection for each segment. Each matrix switch has an address encoder provided, one of which is shown in the right hand diagram. In the address encoder, a magnetic core is provided for each output and a group of seven sense wires are wound through the cores to identify the selected X or Y wire from the selected matrix switch. Sense wires ABC identify the selected matrix switch while sense wires 1, 2, 4, 8 identify the selected X or Y wire therefrom. The encoders associated with MS-7, MS-6, MS-5 etc. have the sense wires ABC, BC, AC etc., respectively, passing through all of the cores of the associated encoder. Additionally, sense wires 1, 2, 4, 8 are wound similarly through the cores of each encoder. Hence, the core associated with output line 15 has sense wires 1, 2, 4, 8 passing through it, the core associated with output line 14 has sense wires 2, 4, 8 passing through it, etc.

The address stored in the memory address register is decoded to cause the matrix switch to apply X or Y drive current to the selected line causing the associated magnetic core to be switched. The outputs from the sense amplifiers connected to the encoder are applied to the compare circuit where they are compared with the outputs of the memory address register. If they are equal, it indicates that the proper mem...