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Gray Code Counter

IP.com Disclosure Number: IPCOM000098880D
Original Publication Date: 1958-Aug-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Halpern, P: AUTHOR

Abstract

This is a Gray code counter wherein only one column of the code changes its value every time the number is changed one unit. The counter includes a register such as one employing three trigger circuits T(1), T(2), and T(3), center right, each of which is set and reset by information comprising logical functions of clock pulses and the output pulses of the other triggers. The left-hand figures represent the gates which develop at their output terminals designated set information S(1) and reset information R(1) for application to the trigger circuit T(1). Each gate comprises two parallelconnected current-switching blocks, each including three transistors in parallel which serve as OR circuits and have their emitters connected to two transistor inverters that have a collector output circuit.

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Gray Code Counter

This is a Gray code counter wherein only one column of the code changes its value every time the number is changed one unit. The counter includes a register such as one employing three trigger circuits T(1), T(2), and T(3), center right, each of which is set and reset by information comprising logical functions of clock pulses and the output pulses of the other triggers. The left-hand figures represent the gates which develop at their output terminals designated set information S(1) and reset information R(1) for application to the trigger circuit T(1). Each gate comprises two parallelconnected current-switching blocks, each including three transistors in parallel which serve as OR circuits and have their emitters connected to two transistor inverters that have a collector output circuit. Similar gates (not shown) are employed for the trigger circuits T(2) and T(3) and interconnections, which have been omitted to simplify the representation,

are made between correspondingly designated terminals of the trigger circuits and the gates.

C and bar C represent the up and down conditions of the clock pulses applied to the designated terminals of the gates, while T(1), T(2), and T(3) represent binary ones and T bar(1), T bar (2), and T bar(3) represent binary zeros present in the indicated sections of the trigger circuits. The clock pulses initiate the application of the designated information to the base-input terminals of the upper left gate and estab...