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Core Tester

IP.com Disclosure Number: IPCOM000098885D
Original Publication Date: 1958-Aug-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Healey, JF: AUTHOR [+2]

Abstract

The schematic circuits of a magnetic core tester are shown centrally. At the upper right is a sequence diagram of a testing cycle. At the bottom is a timing diagram illustrating core output voltage vs. time. A driver trigger provides strobing pulses through delay lines to sample detectors 1 through 4 and also initiates operation of the core driver which in turn drives the test core into its ZERO magnetic state, the core having previously been set in its ONE state by circuitry not shown. The testing cycle begins by resetting all flip-flops as indicated in the sequence diagram. The amplified output of the core, as shown in the timing diagram, is applied to one of the inputs of detectors 1 through 5. Detector 5 in response to that output complements FF(5) to its ONE state.

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Core Tester

The schematic circuits of a magnetic core tester are shown centrally. At the upper right is a sequence diagram of a testing cycle. At the bottom is a timing diagram illustrating core output voltage vs. time. A driver trigger provides strobing pulses through delay lines to sample detectors 1 through 4 and also initiates operation of the core driver which in turn drives the test core into its ZERO magnetic state, the core having previously been set in its ONE state by circuitry not shown. The testing cycle begins by resetting all flip-flops as indicated in the sequence diagram. The amplified output of the core, as shown in the timing diagram, is applied to one of the inputs of detectors 1 through 5. Detector 5 in response to that output complements FF(5) to its ONE state.

Detectors 1 through 4 are sampled by the delayed strobing pulse at times indicated in the timing diagram. Detectors 1 through 4 include an adjustable biasing arrangement whereby they are conditioned by the core output only when that output exceeds the preset bias. Strobing pulses passed by the detectors 1 through 4 are stretched by single shot circuits whose respective outputs cause FF(1) through FF(3) to be set and

FF(4) to be complemented. Detector 5 responds to a ONE output of the test core to complement its FF(5) to the ONE state and also responds to the disturbed ZERO output, if of sufficient magnitude to again complement its FF(5).

Thus, the AND circuit causes its FF(6) to be com...