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Transistor Transfer Circuit

IP.com Disclosure Number: IPCOM000098887D
Original Publication Date: 1958-Aug-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Abstract

A biased transistor is used in a transfer circuit coupling two cores and the circuit includes a delay portion. The transistor provides a consistent output from such transfer circuit and also prevents the transfer of spurious 1's.

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Transistor Transfer Circuit

A biased transistor is used in a transfer circuit coupling two cores and the circuit includes a delay portion. The transistor provides a consistent output from such transfer circuit and also prevents the transfer of spurious 1's.

When cores I and II are read out by a sensing pulse applied to winding W through line S, core 1, if it is in a 1 state, will be switched and will induce a voltage in output winding W(o) that will be sufficient to overcome the cut-off bias + E being applied to transistor T(1). Conduction of transistor T(1) charges capacitor C, and upon termination of the sensing pulse, capacitor C will discharge through W(1) on core II to read a 1 into core II.

Voltage source E can be adjusted to vary the maximum 0 disturbance that can be tolerated by transistor T(1) and the transistor also acts to prevent back discharge of capacitor C through W(o).

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