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Variable Frequency Clock Check

IP.com Disclosure Number: IPCOM000098902D
Original Publication Date: 1958-Oct-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Hill, TW: AUTHOR

Abstract

In machines where binary information is handled a 1 bit is a wide pulse during a bit period, and a 0 bit is the absence of the pulse in the bit period. The 1 bits are usually detected by gating the pulses with pulses from a clock. When the information source supplies the 1 bits at a rate varying within prescribed limits around a fixed frequency, a variable frequency clock, which is controlled by the rate of the incoming pulses, is utilized.

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Variable Frequency Clock Check

In machines where binary information is handled a 1 bit is a wide pulse during a bit period, and a 0 bit is the absence of the pulse in the bit period. The 1 bits are usually detected by gating the pulses with pulses from a clock. When the information source supplies the 1 bits at a rate varying within prescribed limits around a fixed frequency, a variable frequency clock, which is controlled by the rate of the incoming pulses, is utilized.

The variable frequency clock operates so that it continuously produces sharp pulses which should occur, in time, in the center of the wide information pulse. Errors, such as 1 bits detected as 0 bits, may occur either if the variable frequency clock is not operating or if the clock is out of synchronism with the incoming pulses. In order to check that the variable frequency clock is in synchronism with the information, it is necessary to determine if each time a 1 pulse is read from the information source, a clock pulse is present.

The lagging portion of the information pulse is used to sample the presence of both the clock pulse and the information pulse. The leading edge of the read pulse is fed to a phase inverter which has an in-phase output and an out-of- phase output. The out-of-phase output lead, which is connected to one input of an AND circuit, goes negative. The in-phase output lead goes positive, but this positive shift is fed through a very Short delay circuit before being fed to an e...