Browse Prior Art Database

Shift Counter

IP.com Disclosure Number: IPCOM000098946D
Original Publication Date: 1962-Feb-01
Included in the Prior Art Database: 2005-Mar-08
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Berger, R: AUTHOR

Abstract

Three stages of a binary counter utilizing magnetic cores are arranged to count down by one each time the counter is stepped.

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Shift Counter

Three stages of a binary counter utilizing magnetic cores are arranged to count down by one each time the counter is stepped.

There are four, square hysteresis loop cores in each stage. The lowest order stage contains a 1 if core 1 is set and a 0 if core 2 is set. Cores 3 and 4 temporarily store the contents of this stage during the stepping operation. The sensing transistors 5...8 are controlled by windings T. They conduct only during the resetting of their corresponding cores. Current in windings R cause the corresponding core to reset and current in windings W cause the core to be set.

To cause the counter to step down by one, a STEP pulse is applied to the R winding of cores 1 and 2. If the lowest order bit is 0, i.e., core 2 is set before the STEP pulse is applied, the pulse resets core 2. This turns on transistor 6, the collector current of which sets core 4 and attempts to reset both of the corresponding cores 10 and 20 in the next higher order stage. Thus, the contents of that stage are transferred into cores 30 and 40.

After an appropriate delay, a RESET pulse is applied to the lowest order bit and transistor 8 conducts, causing core 1 to be set and attempting to reset cores 30 and 40. Since a carry pulse was propagated between stages, core 30 or 40 had been set and upon resetting causes the second lowest order stage to be complemented. Also, a reset pulse is propagated to the corresponding cores in the next higher order stage.

If core 1 wa...