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Method to detect reset or init condition on a PC motherboard without compromising the signal quality requirement of these GTL signals

IP.com Disclosure Number: IPCOM000099018D
Original Publication Date: 2005-Mar-09
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Abstract

Traditonally in PC / Server Motherboards the GTL signals like RESET and INIT on the Processor BUS are buffered by Level Translators and then connected to an external interface like a system management controller. The system managment controller then performs specific system related tasks based on the condition of these signals. With faster rise times on these signals, and the increasing Front Side Bus frequencies along with the maximum routing length restrictions and minimum stub requirements mandated by the Platform Design guides, it is extremely important to minimize the effect on the signal quality of these signals and adhere to the guidelines. The problem with tapping these signals is more pronounced on multiprocessor systems because, the transmission line effects caused by adding additional loads like buffers, could result in the processors not latching the reset signal on the same clock edge. This will end up in system not working. This invention will solve the afore mentioned problem by avoiding the need for level translation and preserving the original routing guidelines provided by the chipset vendor. This will also eliminate the need for additional simulation to check if the timings are met.

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Method to detect reset or init condition on a PC motherboard without compromising the signal quality requirement of these GTL signals

     The Core idea of the invention is to use the I/O bus like the Low Pin Count Bus or the X-BUS and monitor the Reset Vector fetch from the Processor to determine if the processor is coming out of reset and init. The advantages in using this solution are the elimination of the GTL level translators and also avoiding additional stubs on these signals and also meet the requirements laid out by the Chipset Vendor in their platform design guide. This provides a clean way of verifying if the system is coming out of reset and a latched signal could be used to inform the System management controller for necessary action. The main advantage of this solution is in a multiprocessor environment where the number of loads that could be connected to the RESET and INIT signals is mandated by the processor and chipset vendors.

     This method takes advantage of the fact that when the processor issues a fetch instruction for the reset vector, the South bridge forwards this cycle on its I/O bus which is typically the Low Pin Count Bus on the newer systems or the X-Bus on the older systems. If the system management controller has a similar interface and it is connected to the same BUS, then it should be able to decode the cycle to determine if the processor has issued a fetch from the reset vector. Otherwise, a CPLD can be used Also the I/O port 0x80 access...