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Variable Interlace Circuit for Displays

IP.com Disclosure Number: IPCOM000099040D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Morrish, AJ: AUTHOR

Abstract

An interlace circuit for a raster-scanned CRT display gives an adjustable delay in a vertical ramp waveform to provide interlace adjustment. A conventional vertical oscillator has an additional variable resistor which is switched in series with a timing capacitor by an odd/even interlace signal. This introduces an adjustable time delay in alternate ramp waveforms. It is sometimes a requirement in interlaced raster displays to have an adjustment that can be used in conjunction with an interlace signal to alter the spacing between odd and even field lines for precise interlace in the presence of noise, etc. The disclosed circuit is based on an oscillator commonly used to generate the vertical time base for displays and televisions, etc., and available in integrated circuit form.

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Variable Interlace Circuit for Displays

An interlace circuit for a raster-scanned CRT display gives an adjustable delay in a vertical ramp waveform to provide interlace adjustment. A conventional vertical oscillator has an additional variable resistor which is switched in series with a timing capacitor by an odd/even interlace signal. This introduces an adjustable time delay in alternate ramp waveforms. It is sometimes a requirement in interlaced raster displays to have an adjustment that can be used in conjunction with an interlace signal to alter the spacing between odd and even field lines for precise interlace in the presence of noise, etc. The disclosed circuit is based on an oscillator commonly used to generate the vertical time base for displays and televisions, etc., and available in integrated circuit form. This basic circuit (excluding R2 and S) is shown in Fig. 1, and associated voltage waveforms across C1 and C2 are illustrated in Fig. 2. Two capacitors are used: C1 as part of the timing circuit and C2 as the ramp integration capacitor. At time t0, C1 is fully charged by switchable voltage source V1 to potential V1 and C2 is charged to the same voltage by I2. As the voltage on C2 rises above that on C1, the comparator P switches off the sources and the voltages on both capacitors fall. C2 is linearly discharged by I3, giving the deflection ramp waveform. C1 discharges exponentially to the voltage, V2, set by external variable resistor R1. At time t1,...