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Automatic Generation of Virtual Prototypes

IP.com Disclosure Number: IPCOM000099049D
Published in the IP.com Journal: Volume 5 Issue 4 (2005-04-16)
Included in the Prior Art Database: 2005-Apr-16
Document File: 3 page(s) / 53K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

A Virtual Prototype (VP) is a simulation model of a hardware system which allows exploring design alternatives, testing for requirements correctness and early removal of design errors through simulation. For the generation of a VP, so called Virtual Prototyping, for a signal processing system, an algorithmic description of the system has to be transformed to a VP. Up to date, Virtual Prototyping has been performed manually meaning that there has been no way to transfer the algorithmic description to a VP implementation. Especially for a large SoC (System On a Chip) this task is enormous time consuming and needs additional effort in a development project. This is also an error-prone process, which implies a big amount of verification. A methodology is proposed that allows automatic generation of VPs out of a Synchronous Data Flow (SDF) description. This methodology consists of a system Description Investigator (SDI) which analyzes the algorithm, a Design Database (DDB) which stores the system description and a Virtual Prototype Generator (VPG) which constructs the Virtual Prototype. The entire model is represented in the DDB using the translational tools. After the decisions about which component shall be realized in Hardware (HW) and which in Software (SW) have been made, this information is stored in a file, which is automatically processed by a tool that extends the DDB. It is possible to flag each instance of the system description as HW, SW, or yet UNDEFIENED supporting a future automatic partitioning tool.

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Automatic Generation of Virtual Prototypes

Idea: Martin Holzer, AT-Wien; Bastian Knerr, AT-Wien; Pavle Belanovic, AT-Wien; Prof. Dr. Markus

Rupp, AT-Wien, Guillaume Sauzon, AT-Wien; Dr. Armin Haeutle, DE-Muenchen; Dr. Christian Drewes, DE-Muenchen; Ahmad Sarashgi, AT-Wien

A Virtual Prototype (VP) is a simulation model of a hardware system which allows exploring design alternatives, testing for requirements correctness and early removal of design errors through simulation. For the generation of a VP, so called Virtual Prototyping, for a signal processing system, an algorithmic description of the system has to be transformed to a VP. Up to date, Virtual Prototyping has been performed manually meaning that there has been no way to transfer the algorithmic description to a VP implementation. Especially for a large SoC (System On a Chip) this task is enormous time consuming and needs additional effort in a development project. This is also an error- prone process, which implies a big amount of verification.

A methodology is proposed that allows automatic generation of VPs out of a Synchronous Data Flow (SDF) description. This methodology consists of a system Description Investigator (SDI) which analyzes the algorithm, a Design Database (DDB) which stores the system description and a Virtual Prototype Generator (VPG) which constructs the Virtual Prototype.

The entire model is represented in the DDB using the translational tools. After the decisions about which component shall be realized in Hardware (HW) and which in Software (SW) have been made, this information is stored in a file, which is automatically processed by a tool that extends the DDB. It is possible to flag each instance of the system description as HW, SW, or yet UNDEFIENED supporting a future automatic partitioning tool.

A DSP (Digital Signal Processor) structure enriched by peripheral HW accelerators communicating via a common bus was selected for the design requiring the VP to reflect the DSP as well as to support its peripheral communication. In order to build such a VP, an object-oriented environment in C++ has been created, containing classes for blocks, ports, intercommunication FIFOs (First In First Out), and scheduling, the so-called VP infrastructure of the peripheral (Fig. 1).

The VP peripheral just mimics the exact HW behavior at the bus interface. The internal implementation details (FIFOs, scheduler) are only utilizable in HW with reservations. While this implementation implies a specific HW platform, much importance was put on the fact that this platform is rather general, a DSP with a common bus structure for its HW accelerator units as it is typically used in wireless SoCs designs.

For each module that will be implemented in HW, a C++ file pair is created automatically, consisting of header and class file. These module classes are derived from the CDLBlock class, which is the centre of the VP peripheral infrastructure.

Each derived class instantiates its...