Browse Prior Art Database

SMT Land Grid Array Socket with Integrated Retention for Leadless Chip Carrier Packages

IP.com Disclosure Number: IPCOM000099054D
Publication Date: 2005-Mar-10
Document File: 4 page(s) / 203K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that adds a large SPI flash component to the platform to accommodate the additional memory requirements for PROActive technology. Benefits include minimizing overall platform costs.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

SMT

Land

Grid Array Socket with Integrated Retention for Leadless Chip Carrier Packages

Disclosed is a method that adds a large SPI flash component to the platform to accommodate the additional memory requirements for PROActive technology. Benefits include minimizing overall platform costs.

Background

Current motherboard architecture requires separate components that store the BIOS code and the instructions supporting LAN (Local Area Network) functionality. The BIOS provides the basic instructions for a PC's hardware, and is coded into the computer's ROM. Currently this ROM chip is packaged in a 32-pin Plastic Leaded Chip Carrier (PLCC) and is commonly referred to as the Firmware Hub or Flash chip. This device is based on a bus architecture called a Low Pin Count bus (LPC). The LAN Electrically Erasable Programmable Read-Only Memory (EEPROM) that stores the LAN code is packaged in an 8-pin Small Outline Integrated Circuit (SOIC) package.

There is currently an effort underway to combine these two devices into one package. Motivated primarily by cost savings, this new package would be an 8-pin SOIC. In addition, the bus architecture would change to a proprietary interface know as an Serial Peripheral Interface (SPI). Transition to this new component and architecture is targeted for products that are launching
in 2005. 

Using a socket as an interposer for the Firmware Hub is important during the early stages of motherboard development, since the BIOS is rapidly evolving during this time. Each time that the BIOS code changes, the Firmware Hub must be reprogrammed. There are times when the BIOS is not stable enough to program on the board. When this is the case, the part must be removed, programmed, and then reattached to the board. This process can be very time consuming and cumbersome if the component is soldered directly to the board. Having a socket on the board allows for the simple removal and reattachment of the Firmware Hub. A socket helps expedite this process and is seen as a critical part of motherboard validation.

General Description

The disclosed method accommodates a leadless package that has a total of eight peripheral I/O, as well as a center grounding pad. Figure 1 shows an example of a leadless package used in conjunction with this socket.  Since the I/O contacts are located on the bottom of the package, the socket is designed to make contact with the pads in this configuration. Figure 2 shows one implementation with contacts embedded in the base plastic, which contact the package when it is located in close proximity to the socket base.  These contacts are designed to allow for flexure in the Z-axis (i.e. vertical). This spring affect provides two benefits. First, it compensates for tolerances between components manufactured by one vendor. In addition, it accommodates packages manufactured by different vendors, which might have slightly different nominal dimensions. The contact design ensures optimum flexibility by accom...