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Browse Prior Art Database

Programmable Address Decoder

IP.com Disclosure Number: IPCOM000099123D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Winlow, T: AUTHOR

Abstract

In microprocessor systems there is often a amount of 'Glue' logic. Its functions are to the address decode function for memory and I/O chips to give higher electrical drive capability. In the BICMOS type technologies will remove the need for but the address decoder function will remain. This because the manufacturer of the I/O chips must make it for the system designer to set the address of the chip depending on the application and so he cannot an address decoder within the chip and keep it purpose.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Programmable Address Decoder

       In microprocessor systems there is often a amount of
'Glue' logic.  Its functions are to the address decode function for
memory and I/O chips to give higher electrical drive capability.  In
the BICMOS type technologies will remove the need for but the address
decoder function will remain.  This because the manufacturer of the
I/O chips must make it for the system designer to set the address of
the chip depending on the application and so he cannot an address
decoder within the chip and keep it purpose.

      This combination of chip and system design allows the decoder
to be incorporated inside the I/O device but I/O chip to remain
general purpose.  The cheapness of technology used for VLSI
peripheral chips means that solution should be less expensive than
the current but, perhaps more importantly, it will be to reduce the
card area needed.  This is becoming important as the demand for
minimum size is increasing. 

                            (Image Omitted)

      The basic idea is that the processor sets up the address of
each peripheral chip during its bootstep sequence, immediately after
power-up.  The FIRST 'WRITE' performed by the micro are reserved for
set up the addresses.  On receipt of 'Write' instructions, the chips
set up internal address decoders so that in accesses they will
respond to a particular  The address to which a chip will respond is
the which was on the micro's address bus during the write which set
it up.  The operation is illustrated in the two sections which
describe possible logic

      A possible implementation is shown in Fig. 1.  The logic the
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