Browse Prior Art Database

Limiting Timing Analysis to Consistent Paths

IP.com Disclosure Number: IPCOM000099136D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Bahnsen, RJ: AUTHOR [+3]

Abstract

Disclosed is a method for finding the logically path with maximum delay through a network of logic elements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Limiting Timing Analysis to Consistent Paths

       Disclosed is a method for finding the logically path with
maximum delay through a network of logic elements.

      The Basic Technique: gates are assumed to have unit delay.
Each is associated with a series of logical  Each expression
represents the value of the at a particular time.  The expressions
are built from representing the values of the primary of the
combinational circuit, e.g., A, B. constants 1 and 0. special symbol,
X, representing an unknown  representing logical operators AND, OR
and

      The series of expressions are assigned to nets by the rules:
        The first expression in each series represents the
        value of a net at time = 0, and each succeeding
        expression in a series represents the value of the
        net at 1 time unit after its predecessor.
        All primary input nets get the simple expression
        for that primary input value at time 0 and all
        later times.
        All other nets are the outputs of gates fed by
        other nets.  Let C be the output of a gate with
        logical function F, by nets A and B.  Then, for
        all times T >  = 0, the expression for C at time T
        is the logical function F applied to the
        expressions for A and B at time T-1.
        Every net has the expression "X" for all negative
        times.
   The X value obeys the rules
            X = X
        0 & X = 0
        1 & X = X
        X & X = X
        0   X = X
        1   X = 1
        X   X = X

      Finally, for each primary output net, starting from the
expression in the sequence, some kind of Boolean solving algorithm,
e.g., [*], is used to discover any combination of primary input
values that can the expression to reduce to X.  The time of the
expression in the sequence that can never be an X the actual delay to
that primary output.

      Nominal Delay: C be the output of a gate with logical function
F, by nets A and B.  Suppose that this gate has delay D. for all
times T  = 0, the expression for C at time T the logical function F
applied...