Browse Prior Art Database

BUS Stuck-Fault Algorithm

IP.com Disclosure Number: IPCOM000099141D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 183K

Publishing Venue

IBM

Related People

Berglund, NC: AUTHOR [+2]

Abstract

Stuck faults are faults that persist across operations which are consequently repeatable. faults are characterized as stuck at zero (SA0) or at one (SA1). A stuck fault may appear to be because the conditions which cause the fault to detected are not easily repeated. Some stuck faults are to because of their data-dependent nature and because location of the physical fault is not correlated to the of the symptoms it creates, i.e., a fault appears be associated with a single IOBU, but is not because IOBUs use different addresses, data, and status. These will cause failure of certain commands, certain or total failure of all operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 37% of the total text.

BUS Stuck-Fault Algorithm

       Stuck faults are faults that persist across operations
which are consequently repeatable. faults are characterized as stuck
at zero (SA0) or at one (SA1).  A stuck fault may appear to be
because the conditions which cause the fault to detected are not
easily repeated.  Some stuck faults are to because of their
data-dependent nature and because location of the physical fault is
not correlated to the of the symptoms it creates, i.e., a fault
appears be associated with a single IOBU, but is not because IOBUs
use different addresses, data, and status.  These will cause failure
of certain commands, certain or total failure of all operations.
Consequently, is unable to execute bus commands to collect the status
required to identify the cause of bus  This class of faults must
typically be repaired trial and error removal of cards until the
fault is  It is desirable to minimize the trial and error by
utilizing software algorithms to directly the fault or to at least
identify the board the fault.

      This method utilizes bus commands to detect the of stuck faults
on the bus, independent of bus This algorithm is used as a first step
in program load (IPL) to eliminate data-dependent which will
otherwise occur at varying steps in the process.  This algorithm is
also the basis for more algorithms to reduce the amount of trial and
error removal necessary to identify the cause of failures in
operational environment.

      The algorithm is best understood by first considering a
configuration.  The figure illustrates the flow of  Step 2 is
bypassed for a one-board

      The bus is brought into operation initially, or restored
operation, after a failure by the activation and of BUS CLEAR.  This
is necessary to reset any bus sequences which were left incomplete
when the was re-IPLed or a failure caused cessation of bus  The
activation of BUS CLEAR also causes all to enter the disconnect
state.  This prevents the of all signals toward the BCU and,
consequently, failures on remote boards from disrupting on board 0.

      The key step in stuck-fault testing is accomplished when BCU
issues a Unit Reset.  Unit Reset here causes all origin/destination,
and address data bits to simultaneously tested for SA0.  The command
code for Unit is FF.  The O/D bus is normally unused during Unit but
can be set to 1F with no ill effects.  The A/D is normally used to
select the IOBU to be reset.  In case an A/D field of all ones is
used.  Under normal this would be an illegal use of Unit Reset and
cause all IOBUs on board 7 to be selected and reset; is not the
desired effect since we simply want to test stuck faults, not to
reset an IOBU (thereby losing its state).  Since there is no board 7
in the one case, no IOBUs are selected or reset, but all check parity
errors during the bus select cycle.  The net of execution of Unit
Reset in this case is an bus timeout no slave will respond to the
command.  T...