Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Power Control Sequencing and Fault Program

IP.com Disclosure Number: IPCOM000099142D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Rohulich, AS: AUTHOR [+2]

Abstract

A microprocessor control program for processor sequencing and fault isolation comprises means for proper logic card plugging, power supply standard power interface sequence, power warning PS1-PS3 operation, and operation and checking of processor controller or support processor status. error conditions are detected by the program, and error fault code data is made in four bits of an 8-bit communications bus

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 82% of the total text.

Power Control Sequencing and Fault Program

       A microprocessor control program for processor sequencing
and fault isolation comprises means for proper logic card plugging,
power supply standard power interface sequence, power warning PS1-PS3
operation, and operation and checking of processor controller or
support processor status. error conditions are detected by the
program, and error fault code data is made in four bits of an 8-bit
communications bus

      The figure depicts a higher level flow chart wherein the blocks
show actions taken and the diamond-shaped show decisions made.
Beginning with a RAM TEST to whether the RAM is "good", using pre-set
values, a is made at 10.  A NO here causes a fault signal, a YES
allows the sequence to continue.  A ROM TEST is against pre-set
values which, if NO, causes a fault but if YES, the sequence
continues after a delay (5 for example) to permit the power switch 11
to be ON.  Now, with power applied to the microprocessor, are tested,
faulty sensors will be OFF and good will be ON, a decision being made
at 12.  Next, the relay K1 is picked which applies power to Power
Supply (PS1) and to Power Supply 3 (PS3).

      A fault in either power supply causes a fault signal, if a
decision at PS1 and PS3 GOOD is YES, a Support (SP) Reset signal is
initiated to start the SPI Power Interface) 13 sequence to determine
whether I/O connections are operable.

      Finally, a Monitor Routine 14 is entered where the Proce...