Browse Prior Art Database

Circuit to Reduce Format Times of Disk Drives

IP.com Disclosure Number: IPCOM000099147D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 78K

Publishing Venue

IBM

Related People

Lochner, DL: AUTHOR

Abstract

A technique is shown which allows a National DP-8466 "Disk Data Controller" (DDC) circuit module to perform a Track Format in a single revolution on a disk file having the Small Disk Interface (ESDI). The method adds a which deactivates "Write Gate" to the file for a interval between the "ID" and "data" fields of each during a Format operation. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Circuit to Reduce Format Times of Disk Drives

       A technique is shown which allows a National DP-8466 "Disk
Data Controller" (DDC) circuit module to perform a Track Format in a
single revolution on a disk file having the Small Disk Interface
(ESDI).  The method adds a which deactivates "Write Gate" to the file
for a interval between the "ID" and "data" fields of each during a
Format operation. 

                            (Image Omitted)

      One possible implementation of this technique is shown the
circuit of Fig. 1, consisting of Programmable Logic (PLA) 1 and
Counter 2, which contains both a counter and an input register.  In
Fig. 1:
   The signals +DDC READ CLOCK, +DDC WRITE GATE, and
   +DDC WRITE DATA are outputs from the DDC module.
   The Signals -ENABLE, -READ REGISTER, +LOAD REGISTER,
   and DATA BUS 0-7 are from a controlling microprocessor.
   The line +SECTOR PULSES is a file output which
   identifies the start of each Sector.
   The circuit output, -FILE WRITE GATE, drives a file
   input.

      Before a Format operation is started, a controlling loads the
input register portion of Counter 2 a value calculated from ID field
parameters, thus the DDC module's ability to define a variety of
field formats.  When Counter 2 is not counting, its portion is held
in Load mode by a PLA output, to the value in the input register into
the Counter.

      In operation, for each Sector, the circuit monitors the Write
Data sig...