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High Gain Small Signal Receiver

IP.com Disclosure Number: IPCOM000099177D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Banker, D: AUTHOR [+3]

Abstract

A circuit is disclosed that accepts small signal and utilizes high performance PNP transistors. The shown in the figure has an internal reference bias is used for the current switch. The reference bias is used to generate a bias voltage through T9 for the PNP T6 and T8 used to sink the current from the current source.

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High Gain Small Signal Receiver

       A circuit is disclosed that accepts small signal and
utilizes high performance PNP transistors.  The shown in the figure
has an internal reference bias is used for the current switch.  The
reference bias is used to generate a bias voltage through T9 for the
PNP T6 and T8 used to sink the current from the current source.

      The push-pull output operation provides high gain for phases,
thereby providing performance enhancement in to small signal swing
operation.  Transistors T3, and transistor T11 provide a constant
current source and for T5 and T7.  This current from T3 and T5 is
directed the input devices T1 and/or T2 when their respective are at
an 'up' level.  At this time, current from T4 T7 will be directed
through T8.  This condition will a 'down' level at the 'NOR' output,
and an 'up' at the 'OR' output.  If both inputs (In1 and In2) are a
'down' level, the NOR output will be at an 'up' level the OR output
will be at a 'down' level.  This occurs current through T3 and T5
will be directed through and current from T4 and T7 will be steered
through T2. T14 and T16 together with resistor R3 establish positive
current source which provides the mirror current T11.

      Transistors T12, T13, and T15 together with R2, R1 and
respectively, provide negative current sources for the  The circuit
performs NOR/OR logic and has in high performance computing systems.