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New Self-Aligned Pillar CMOS - Structures and Fabrication

IP.com Disclosure Number: IPCOM000099183D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Dhong, SH: AUTHOR [+3]

Abstract

Disclosed is a new self-aligned pillar CMOS technology. The high density pillar CMOS are built on the vertical wall of the pillar selectively grown on the substrate. The NMOS and PMOS are isolated by a thin nitride barrier layer. using the self-aligned technique, the dual-polysilicon the source and drain junctions of the pillar are formed simultaneously. The areas of two and PMOS transistors are merged within the same pillar Thus, the layout of the new pillar CMOS circuits in a smaller planar surface area. The cross section this new pillar CMOS device is shown in Fig. 1.

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New Self-Aligned Pillar CMOS - Structures and Fabrication

       Disclosed is a new self-aligned pillar CMOS technology.
The high density pillar CMOS are built on the vertical wall of the
pillar selectively grown on the substrate.  The NMOS and PMOS are
isolated by a thin nitride barrier layer. using the self-aligned
technique, the dual-polysilicon the source and drain junctions of the
pillar are formed simultaneously.  The areas of two and PMOS
transistors are merged within the same pillar  Thus, the layout of
the new pillar CMOS circuits in a smaller planar surface area.  The
cross section this new pillar CMOS device is shown in Fig. 1.

      The fabrication procedures of the pillar CMOS device are in the
following:

      (1)  Begin with a wafer with p- epi on p+ substrate and shallow
trench isolation regions.  Then deposit and thick layers of CVD
silicon nitride barrier layer. thick oxide layer and nitride barrier
layer which remain then used to make the growth of the selective
epitaxial (Fig. 2).

      (2)  Remove the thick oxide mask layer.  A pillar layer is
formed.  Pattern after suitable steps, then implant to form n-well
and p-well respectively (Fig. 3).

      (3)  Grow a thin gate oxide on the vertical walls of the
structure and on the other area, as required.  A layer is then
chemically deposited over the structure and the surface of the
substrate.  The side polysilicon gate is formed by RIE polysilicon
and oxide proper treatm...