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Logic Circuit Initializer

IP.com Disclosure Number: IPCOM000099188D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

Disclosed is a circuit technique for setting circuits (e.g., registers, latches, etc.) to a state at the beginning of a power- on cycle without need for an external signal - usually referred to as a reset signal.

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This is the abbreviated version, containing approximately 62% of the total text.

Logic Circuit Initializer

       Disclosed is a circuit technique for setting circuits
(e.g., registers, latches, etc.) to a state at the beginning of a
power- on cycle without need for an external signal - usually
referred to as a reset signal.

      The figure shows a schematic of the Logic Circuit  T1, T5 and
T8 are P-channel FETs.  The devices are N-channel.  T2 and T3 have
their tied to their source nodes so that the voltage is zero for all
devices. T6 is operated with a grounded well, its threshold be
several tenths of a volt greater than it would be the case where the
well is tied to node B.

      During the initial part of the VDD ramp up, node A will low to
keep T6 off and T5 will pull node C to VDD.  This insure that Vout
is held at ground level.  In order for to go high, node C must be
pulled below the "switching of the inverter formed by T8 and T9.
This requires T6 and T7 be conducting.  Another way of saying this is
node A must be sufficiently high to provide the and overdrive
voltages (for T6 and T7) needed to node C below the inverter
switching level.  The network through T4 controls the node A voltage.
 By making T2, T3 T4 identical-size devices, the voltage drop across
each will be the same.  Therefore, VA = (2/3)xVD.  Because overdrive
on T1 increases as VDD increases, VD will be nearly VDD when the
power supply is near its final  Therefore, VA approaches (2/3)VDD
which is to insure Vout going to its high state. and T6 form a "log...