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On-Chip Implementation of a CMOS Encoder

IP.com Disclosure Number: IPCOM000099190D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Stakely, BL: AUTHOR

Abstract

This article describes a method of implementing a Encoder in a CMOS process. In this encoding a binary signal is turned into a tertiary signal. extra complexity required in the receiver due to the signal level is traded against the increased signal due to the negation of the Nyquist sampling The is due to the intentional introduction of interference.

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On-Chip Implementation of a CMOS Encoder

       This article describes a method of implementing a Encoder
in a CMOS process.  In this encoding a binary signal is turned into a
tertiary signal. extra complexity required in the receiver due to the
signal level is traded against the increased signal due to the
negation of the Nyquist sampling  The is due to the intentional
introduction of interference.

      Fig. 1 shows the block diagram of a transversal filter is used
to implement the Duo-Binary Encoding scheme. 2 shows the on-chip
implementation.  From Fig. 1, the taps have a weighting of 1.  By
adding the various of 1's and 0's, it is seen that 3 signal levels
needed.

      With reference to Fig. 2, D-Latch 10 implements the block in
Fig. 1.  By trying the various combinations 1's and 0's at the
D-Latch ports, it is seen that three states result.  The first state
occurs when the CMOS (T2 and T3) is open and T1 pulls the output to
VDD. second state occurs when the switch is closed and T4 is  In this
case, T1 in conjunction with T5 holds the at VDD/2.  The third state
occurs when the CMOS is closed and T4 is on.  T4 is sized such that
the is pulled to ground.  From this discussion, a binary is changed
to a tertiary signal and the block diagram Fig. 1 has been
successfully implemented.