Browse Prior Art Database

Programmable Timing Control

IP.com Disclosure Number: IPCOM000099191D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR [+2]

Abstract

A programmable pulse generator is a logic block receives two timing parameter codes: the D-code for and the W-code for Width. See Fig. 1. D-code and are presented to the pulse generator via the TP Parameter) bus at different times. The waveforms in 2 show an example of D=3 and W=4. Vertical lines clock periods. The START signal acts as a timing D cycles (as specified in the D-code) after the signal has gone high, the OUTPUT signal is activated remains active for W cycles (as specified by the The D-code and the W-code need not be provided to pulse generator simultaneously, and hence they can time the TP bus.

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Programmable Timing Control

       A programmable pulse generator is a logic block receives
two timing parameter codes:  the D-code for and the W-code for Width.
 See Fig. 1.  D-code and are presented to the pulse generator via the
TP Parameter) bus at different times.  The waveforms in 2 show an
example of D=3 and W=4.  Vertical lines clock periods.  The START
signal acts as a timing  D cycles (as specified in the D-code) after
the signal has gone high, the OUTPUT signal is activated remains
active for W cycles (as specified by the  The D-code and the W-code
need not be provided to pulse generator simultaneously, and hence
they can time the TP bus.

      The timing shown in Fig. 2 can be done by the logic in Fig.
3.  The contents of the Counter and the Latch are first reset to
zeros (as will be shown the reset will be done automatically at the
end of operation).  The D-code is first gated into an m-bit (m=6 in
this example) via the TP Bus by the START  D must be equal to or
larger than one.  The maximum allowed is determined by the size of
the counter.  Each clock pulse (not shown) causes the counter to
count by one so long as the decrementing signal, DECR, is  In fact,
DECR remains one unless the count has reached  As is shown below, the
count reaches zero only when W-code has been counted down to zero,
because the W-code loaded into the counter immediately after the
D-code has counted down to the value of one.

      After the D-code has been loaded into the counter, B1 remains
ONE until count=1 is reached.  At that bit positions C2, C4, C8, C16,
and C32 of the counter all zeros, causing B1 to go to zero.  At
count=1, C1 is one which causes OT to go to one. ...