Browse Prior Art Database

Lsi Packaging Design

IP.com Disclosure Number: IPCOM000099199D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Lemon, GK: AUTHOR [+4]

Abstract

Disclosed is a high chip density, stabilized thin carrier technique that is attached to a stabilized board for I/O and power distribution, as shown in figure. Chip join, chip burn-in and preliminary testing performed on the semiconductor chips on the thin film prior to mounting to the circuit board. Therefore, circuit board is only subjected to eutectic solder Thin copper/INVAR* copper planes two and thousandths of an inch thick are used to stabilize or the assembly coefficient of thermal expansion. These replace normal copper ground and power planes used in boards. This technique provides a C4 compatible, area chip assembly for future packaging requirements.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Lsi Packaging Design

       Disclosed is a high chip density, stabilized thin carrier
technique that is attached to a stabilized board for I/O and power
distribution, as shown in figure.  Chip join, chip burn-in and
preliminary testing performed on the semiconductor chips on the thin
film prior to mounting to the circuit board.  Therefore, circuit
board is only subjected to eutectic solder  Thin copper/INVAR* copper
planes two and thousandths of an inch thick are used to stabilize or
the assembly coefficient of thermal expansion.  These replace normal
copper ground and power planes used in boards.  This technique
provides a C4 compatible, area chip assembly for future packaging
requirements.

      The advantages of this disclosure are as follows:
1)   The multi-layer circuit board is not exposed to chip
     join temperature (350oC); therefore, lower temperature
     dielectrics can be used.
2)   Circuit board reliability will be significantly
     improved.
3)   Chip burn-in and testing will be done at the thin film
     level.
4)   The thin film carrier can be optimized to attach both
     silicon and galium-arsenide chips.
5)   The thin film process is compatible with continuous
     roll, high volume manufacturing.
*  Trademark of IMPHY S.A., Paris, France.