Browse Prior Art Database

Computer System Performance Utilizing Direct Memory Access Byte Alignment

IP.com Disclosure Number: IPCOM000099204D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 96K

Publishing Venue

IBM

Related People

Ho, WJ: AUTHOR

Abstract

A technique is described the performance of a computer system is improved by a direct memory access (DMA) byte alignment that is transparent to micro-code. The intent is use a state machine to cover all byte alignment cases so the micro-code is not required to take care of special

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Computer System Performance Utilizing Direct Memory Access Byte Alignment

       A technique is described the performance of a computer
system is improved by a direct memory access (DMA) byte alignment
that is transparent to micro-code.  The intent is use a state machine
to cover all byte alignment cases so the micro-code is not required
to take care of special

      Typically, byte alignment circuitry requires a systems manager
micro-code to take care of special byte situations.  The concept
described herein transparent micro-code alignment that not only
performance but saves memory space required for the micro-code.  The
concept provides the following
        Programmability for both two and four bytes of
        device memory.
        Provides internal registers (read/write) for RAS
        purposes.
        Provides programmable implicit DMA with burst mode
        and memory-to-memory DMA.
        Provides two channels for device memory transfer
        with byte alignment.
        Provides address parity generating function.
        Provides data parity checking/generating function.

      The concept interfaces to the bus control unit, as shown Fig.
1. Implicit DMA of burst mode is used because the is considered much
better than cycle-steal mode. implicit DMA contains byte-alignment
hardware so as to the system memory address to and from the local
memory  It is programmable for bo...