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Versatile Testcase Driver for Simulation

IP.com Disclosure Number: IPCOM000099209D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Bergman, S: AUTHOR [+3]

Abstract

Simulation of several million gate processors on multiple chips is a challenging problem. The amount of simulation required demands that a common format and testcase driver be developed. The driver must enforce the conventions, monitor and be simple to use, yet it must allow flexibility model selection, model stimulation, and results

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Versatile Testcase Driver for Simulation

       Simulation of several million gate processors on multiple
chips is a challenging problem.  The amount of simulation required
demands that a common format and testcase driver be developed.  The
driver must enforce the conventions, monitor and be simple to use,
yet it must allow flexibility model selection, model stimulation, and
results

      The invention disclosed is a testcase driver that these diverse
requirements and more.  A menu system onto the front end allows new
users to proceed, yet more sophisticated users the ability to
simulate the in complicated ways.  The program, called RTPG executive
(RTX), accepts AVPs and all the various of implementing the same
architecture; the program is of supporting several sub-models of each
while the high level architectural view inherent in AVPs.  These
sub-unit models allow solo bring-up of parts of the system at faster
simulation speeds to smaller model sizes.

      The base operation of RTX is to read a testcase, then, on the
testcase, make the appropriate initializations the model, stimulate
the model as it simulates watching the ending conditions to be met,
checking the results in the testcase, and reporting the results to
the and the system monitor.

      Many options are supported by RTX to allow the design to take
on different aspects of the design.  The driver understands the
different level of the hierarchy and allows the user to select where
to load and instructions.  For example, the instruction cache the
data cache directories, the instruction and the data TLBs can be
either loaded automatically full), not loaded or randomly loaded by
the program. is significant since the state of the directories and
can change the character of the testcase (allowing each to be run in
several modes).  Other exa...