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Cascode Voltage Switch True and Generator

IP.com Disclosure Number: IPCOM000099222D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Heudorfer, P: AUTHOR [+2]

Abstract

This circuit provides high speed multiplexing with true and complement outputs and uses a of space. Generation of addresses is accomplished latching the result of a comparison between a logic block a reference block. The reference is enabled every cycle compared to the logic block. The logic block prevails when its output requirements are met, generating a true Whenever the output conditions of the logic block not met, the reference block prevails and generates a address.

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Cascode Voltage Switch True and Generator

       This circuit provides high speed multiplexing with true
and complement outputs and uses a of space.  Generation of addresses
is accomplished latching the result of a comparison between a logic
block a reference block.  The reference is enabled every cycle
compared to the logic block.  The logic block prevails when its
output requirements are met, generating a true  Whenever the output
conditions of the logic block not met, the reference block prevails
and generates a address.

      Referring to the figure, nodes A, B, E, and F are precharged
through devices Tp1, Tp3, Tp9, Tn3 and  When inputs to logic block 2
and reference block 4 are on, nodes E and F are pulled down.  Device
Tn3 is in channel length against Tn4 which allows node A fall before
node B, thus setting the latch.  With node A and node B high, output
is a true address at T.  When are not met in logical function 2,
reference block takes over.  Node F falls, node E stays high, device
Tn4 on, and node A is high.  Addresses stay latched until pulse R
fires, precharging nodes A, B, E, and F. Tp7 and Tp8 keep the latch
set when logic inputs to block 2 are removed by keeping nodes E and F
at  Device Tp9 equalizes nodes E and F during the R pulse.  When the
restore pulse is off, devices and Tp11 hold nodes A and B high, which
prevents until an address is selected.  Inverters I1 and I2 the
output at true T and complement C output nodes.