Browse Prior Art Database

Method for Detecting Memory by Mapping All Main Storage Into I/O Space

IP.com Disclosure Number: IPCOM000099223D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 101K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+4]

Abstract

Provides a means for the software to test main for stuck bit faults and to test the error code generation and checking logic for logic during manufacturing test, in power-up diagnostics or field diagnostics.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Detecting Memory by Mapping All Main Storage Into I/O Space

       Provides a means for the software to test main for stuck
bit faults and to test the error code generation and checking logic
for logic during manufacturing test, in power-up diagnostics or field
diagnostics.

      In a processor system where the main storage contains a error
correction, double error detection code, bits of memory per word of
storage are required the error correction code bits.  The ability to
test extra bits of memory along with the error correction generator
and checker is necessary for the diagnostics the machine during
manufacture, initial power-up or for diagnostics.  The design
described in this article allow software to check all of main storage
for stuck faults and, in addition, allows the error correction
generation and checking logic to be tested.

      In a processor that is a cached system, the data flow the main
memory may be as shown in the figure.  The transfers double words of
data with parity to and the data cache on load and and never directly
reads or writes main storage. main memory interface is controlled by
the storage unit and the data cache chips.  When the processor data
from some real address, the data is transferred main memory to the
data cache, if it is not already in cache, where it is checked for
errors, corrected, if then placed in the cache and sent to the  On
stores, the data is stored in the cache and the main memory.  If the
cache is full, then the least used data is removed from the cache and
stored in memory.  With this data flow, the processor has no way
directly access the main memory without the access first through the
data cache.

      The implementation described here gives the processor access to
main storage by mapping all of the storage local I/O space (I/O space
that is reserved for control registers) and adding the necessary
logic to the storage control unit to allow the to do loads and stores
to memory with normal I/O and store commands.  Data is...