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Instruction Fetch Address Implementation

IP.com Disclosure Number: IPCOM000099234D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Grohoski, G: AUTHOR [+2]

Abstract

The Instruction Fetch Address Register (IFAR) is register which contains the next address to be fetched. a processor with an instruction cache and virtual this register is used to hold a 32-bit effective Portions of the register will be used to address registers, TLB congruence classes, cache directory classes and the cache array itself. Typically, is desirable to perform the address translation, the directory tag compare, the fetching of the words from cache and the buffering of those words all in one cycle.

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This is the abbreviated version, containing approximately 56% of the total text.

Instruction Fetch Address Implementation

       The Instruction Fetch Address Register (IFAR) is register
which contains the next address to be fetched. a processor with an
instruction cache and virtual this register is used to hold a 32-bit
effective Portions of the register will be used to address registers,
TLB congruence classes, cache directory classes and the cache array
itself.  Typically, is desirable to perform the address translation,
the directory tag compare, the fetching of the words from cache and
the buffering of those words all in one cycle.

      The access to these arrays must occur very early in the and,
therefore, no combinational logic can exist the register and the
address port to the arrays. timing constraint requires that the cache
reload and certain bus operations that need access to the must act
through the IFAR.  A second register, the shadow (IFARS), is used to
hold the old value of the while these operations are occurring.  When
the IFAR is in the normal fetching operation, the register needs to
updated each cycle to reflect the number of instructions
Unfortunately, the of exactly how many were successfully fetched
buffered occurs very late in the cycle.

      To alleviate the timing problem, four separate are used to
compute the values for IFAR+4, IFAR+12, and IFAR+16 which are
multiplexed and selected based on the number actually fetched. that
there is a maximum of four instructions that can fetched in one
cycle. Since no sin...