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Optimized VLSI CMOS Bypass

IP.com Disclosure Number: IPCOM000099236D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Krauter, BL: AUTHOR [+2]

Abstract

Disclosed is the optimum substrate and device well that retains the inherent bypass characteristics of CMOS, yet solves its resonant noise problems.

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This is the abbreviated version, containing approximately 81% of the total text.

Optimized VLSI CMOS Bypass

       Disclosed is the optimum substrate and device well that
retains the inherent bypass characteristics of CMOS, yet solves its
resonant noise problems.

      When a VLSI CMOS chip is packaged, its inherent bypass 

                            (Image Omitted)

 (formed by its quiet and device well regions)
is placed in parallel with parasitic inductance.  The combined L-R-C
circuit presents resonant impedance to the active circuits (Fig. 1).
When active circuits switch, the on-chip voltage rings or at the
natural or resonant frequency of the L-R-C  This noise can be
controlled by designing a loss into the substrate and device well
regions.

      Circuit capacitances do not, in general, close directly the
chip power supply terminals.  Most circuit close on either the chip
substrate or the wells.  These capacitances have larger resistive
back to power and ground.  These resistive paths can widely varied
without affecting functional circuit speed.

      With respect to resonant noise, the inherent bypass of a VLSI
CMOS chip cannot be modeled as a R-C circuit.  At least two R-C
networks are needed. first models circuit capacitances that close
directly on power supply terminals.  The second models circuit that
close on either the chip substrate or the wells.

      The second R-C network can be tuned to minimize overall
impedance, and again this tuning does not affect speed.  The second
R-C...