Browse Prior Art Database

Memory Controller Which Adjusts to Changes in System Rate

IP.com Disclosure Number: IPCOM000099238D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Hardell, W: AUTHOR [+2]

Abstract

This invention allows memory controllers to adjust to changes in clock rate without or jumpers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 91% of the total text.

Memory Controller Which Adjusts to Changes in System Rate

       This invention allows memory controllers to adjust to
changes in clock rate without or jumpers.

      Many DRAM memory controllers generate their outputs, as RAS,
CAS, WE, and OE, by raising and lowering these at multiples of the
system clock; for example, if needs to be low for 80 ns and the clock
is running at 40 RAS would be lowered at a clock edge and raised two
later.

      If the clock rate can be multiple speeds, the controller be
designed to operate at the fastest possible speed. run at a slower
clock rate, this controller may be slower than necessary, slowing the
overall system  This invention shows how the controller can or
measure the system clock rate and adjust the output to yield optimum
DRAM timings and for several different clock rates.  This method also
be used for other controllers where the outputs to remain constant as
the clock speed changes.

      The counter shown in the figure counts system cycles and reset
to 0 whenever a real-time clock pulse is received. real-time clock
must be much slower than the system such as a refresh clock.  The
count value is compared integer values x and y.  If the system clock
is fast, the will reach    x before it is cleared by the clock.  This
causes the fast signal to be "1", is latched and held at the same
time the counter is  If the counter value is between x and y when the
clock is received, med mode is invoked.  Slow mode...