Browse Prior Art Database

Data Transfer for PIO To/From System Non-Preemptable

IP.com Disclosure Number: IPCOM000099245D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 1 page(s) / 52K

Publishing Venue

IBM

Related People

Arimilli, R: AUTHOR [+3]

Abstract

Programmed I/O(PIO) to/from System Memory is an which was defined to resolve a cache coherency between the processor and a First Party Direct Access(DMA) Master on the MICRO CHANNEL* I/O Bus. the I/O Channel Controller(IOCC) and the processor cached memory which presents an exposure that they have different images of the current memory contents. PIO to/from System Memory (PSM) operation routes the memory acess through the IOCC cache to insure a view of System Memory for the First Party DMA Adapter the processor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Data Transfer for PIO To/From System Non-Preemptable

       Programmed I/O(PIO) to/from System Memory is an which was
defined to resolve a cache coherency between the processor and a
First Party Direct Access(DMA) Master on the MICRO CHANNEL* I/O Bus.
the I/O Channel Controller(IOCC) and the processor cached memory
which presents an exposure that they have different images of the
current memory contents. PIO to/from System Memory (PSM) operation
routes the memory acess through the IOCC cache to insure a view of
System Memory for the First Party DMA Adapter the processor.

      The PSM operation was implemented in the IOCC by the PIO
operation, executing an IOCC controlled transfer, then completing the
PIO Load or Store.  To the it is seen as a special First Party DMA
operation is initiated by the processsor.  The IOCC implements
operation by transferring data from a PIO Buffer to a Buffer(PIO
Writes) or from a DMA Buffer to a PIO Reads). This buffer-to-buffer
transfer is to implement a data alignment function inherent in PSM
operation.  This data transfer is a controlling in determining the
performance of the PSM operation.

      MICRO CHANNEL I/O Bus protocol allows a higher priority to
preempt a device already granted the bus.  The implementation has PIO
on the lowest priority, which potential performance impacts.  PSM
performance were prevented through selective suspension of on the
MICRO CHANNEL I/O Bus.  This is achieved pulling the -BURST signal
w...