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Voltage Reference for Dynamic Control of Complementary Oxide Silicon Drivers

IP.com Disclosure Number: IPCOM000099258D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Taylor, RS: AUTHOR

Abstract

A new circuit provides a reference voltage (Vr) to device current and inversely proportional to oxide capacitance and device threshold voltage. Vr can used directly or converted to a digital signal to control driver (OCD) delay. Separate voltage references be generated that are independently proportional to and P-channel device parameters for independent of rising and falling transitions.

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Voltage Reference for Dynamic Control of Complementary Oxide Silicon Drivers

       A new circuit provides a reference voltage (Vr) to device
current and inversely proportional to oxide capacitance and device
threshold voltage.  Vr can used directly or converted to a digital
signal to control driver (OCD) delay.  Separate voltage references be
generated that are independently proportional to and P-channel device
parameters for independent of rising and falling transitions.

      Referring to the figure, a clock signal is applied to IN of an
inverter comprised of P-type transistor T1 N-type transitor T2.  The
inverter is loaded by thin capacitor C1 which is large enough to
ensure that the at node A does not reach supply voltage levels (VH
ground).  A square wave input at IN results in the wave form shown at
node A.  This signal is applied to gate of N-type source follower T3.
 Voltage Vr at output node OUT is stabilized by capacitor C2 and
bleeder R2.

      The amplitude of the signal at node A is determined by speed
and device current of transistors T1, T2, and the of C1.  Voltage Vr
at node OUT is relatively and is approximately one device threshold
Vt below peak of the waveform at node A.  An increase in the or
device current of transistors T1, T2 or a decrease capacitaance of C1
increases the amplitude of the signal node A and the voltage level of
Vr at node OUT.  A in Vt of transistor T3 does not affect node A
but Vr at OUT.  Therefore, any chan...