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Browse Prior Art Database

Rate of Current Change Off-Chip Driver With Low Shoot- Current

IP.com Disclosure Number: IPCOM000099262D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Erdelyi, CK: AUTHOR [+2]

Abstract

Noise coupled from line to line or through power due to rapid voltage and current changes during device turn-on is minimized by this off-chip driver

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 97% of the total text.

Rate of Current Change Off-Chip Driver With Low Shoot- Current

       Noise coupled from line to line or through power due to
rapid voltage and current changes during device turn-on is minimized
by this off-chip driver

      Referring to Fig. 1, transistors T2, T4, T6, T8, T10, T12 are
output devices.  Each output device contributes fraction of the
output current.  Turn-on of transistors T4 T6 is delayed by buffers
P2 and P3.  Turn-on of T10 and T12 is delayed by buffers N2 and N3.
output voltage swing is accomplished by using transistors T2, T4, and
T6 and N-type transistors T8, and T12.  Momentary short circuit
current from VDD to when output P devices are turning off and N
devices turning on, is prevented by turn-on of transistors T14, and
T18 causing nodes N4, N6, and N8 to rise before N12, N14, and N16 due
to the delay through circuit NL. short circuit current from VDD to
ground when output devices are turning off and P-type output are
turning on is prevented by action of T20, T22, T24 in conjunction
with delay through circuit PL which nodes N12, N14, and N16 to fall
prior to the fall of N4, N6, and N8.  Inverters I2 and I4 and
circuits NL PL further provide logic to ensure that output devices
through T12 are off when ENABLE is down and preventing from changing
the state of the output.
   Fig. 2 shows internal detail of circuits P2 and P3.
   Fig. 3 shows internal detail of circuits N2 and N3.
   Fig. 4 shows internal detail of circuit PL.
   Fig...