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Mechanism for Sharing Interrupts

IP.com Disclosure Number: IPCOM000099265D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 3 page(s) / 132K

Publishing Venue

IBM

Related People

Piazza, WJ: AUTHOR

Abstract

This article describes a mechanism for use in a computer (PC) system which allows two or more which meet certain prerequisites to share an interrupt without the loss of interrupts.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mechanism for Sharing Interrupts

       This article describes a mechanism for use in a computer
(PC) system which allows two or more which meet certain prerequisites
to share an interrupt without the loss of interrupts.

      Conventionally, where an interrupt request signal is a
programmable interrupt controller (PIC) as follows:
1. A latch in the interrupt request register (IRR) within
   the PIC is set.  This latch is only activated by the
   rising edge of the interrupt request line.
2. The PIC internally resolves the priority of this
   interrupt versus other interrupts being serviced and,
   upon deciding that it is appropriate to service this
   interrupt, it functions as follows:
   sets an in-service register (ISR) bit,
   clears the IRR, and
   signals the processor to interrupt its normal instruction
   execution sequence.
3. The "interrupt driver" software, in the process of
   handling the interrupt, will usually perform some
   action (such as reading or writing a register) that
   causes the device to clear its interrupt request line.
4. Later, usually after the interrupt has been completely
   serviced, the interrupt handler issues an "end of
   interrupt" (EOI) command to the interrupt controller,
   which instructs the controller to clear the ISR bit and
   allow additional interrupts on this level and on lower
   priority levels.

      Sharing interrupts under this scheme is not as simple as the
interrupt request lines from two devices together if the two devices
interrupt at nearly identical the following sequence of events may
occur:
1. Device 1 raises its interrupt request and causes the
   IRR bit for that level to be set.
2. Device 2 raises its interrupt request line also.
3. The PIC resolves priorities and decides to service this
   level.
   The ISR bit for this level is set.
   The IRR bit is cleared.
   The processor is notified.
4. The interrupt handler (which may now consist of a
   "chain" of handlers) gets control and tries to
   determine which device caused the interrupt.  This may
   be done by passing control along the chain, and the
   first handler to recognize that the device which it
   services has an interrupt request active may service
   its device and terminate the chain.  The chain may be
   terminated at this point even though there are
   additional devices to consider because the interrupt
   handlers may have originally been written assuming that
   interrupts were not shared and therefore they are the
   only handlers active on this interrupt level.

      When the handler performs the EOI, the ISR bit is cleared
further interrupts may occur.  The problem that device 1 was serviced
and device 2 was is that device 2 is holding the interrupt line and
the edge sensitive latch on the input of the will not respond to it
unless the line is pulled and then high again.

      A number of alternatives have...