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Browse Prior Art Database

Enhanced Overlap by Early EOP Reprioritization of Stores

IP.com Disclosure Number: IPCOM000099283D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 147K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

When there are no hazards that prevent the decoder correctly decoding and queueing instructions, at a time decoding does not limit the overlap possible a machine. The potential overlap achievable can be by early EOP (End OP) of multicycle instructions the reprioritization of their stores.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 50% of the total text.

Enhanced Overlap by Early EOP Reprioritization of Stores

       When there are no hazards that prevent the decoder
correctly decoding and queueing instructions, at a time decoding does
not limit the overlap possible a machine.  The potential overlap
achievable can be by early EOP (End OP) of multicycle instructions
the reprioritization of their stores.

      In a highly overlapped implementation, there are delays allow a
single decode per cycle to provide enough instructions to take
advantage of the parallelism in the rest of the machine.  Examples of
this type delay are:
 1.  Multicycle Execution
 2.  Cache Bus Contention
 3.  Address Generate Interlock
 4.  Operand Store Compare
 5.  Cache Miss for Data

      Branch delays associated with BWG (Branch Wrong Guess) a BHT
(Branch History Table) are not in this category.

      Some of the examples can take advantage of the ability do
out-of-sequence operand activity.  All of them will instructions even
in the absence of this capability.  Consider execution of a sequence
of instructions, A through N, with the ability to EOP two at a time.
The time between DECODE (A...N) and (!) has by the point of N's EOP
(!) been reduced to what would have been if A had been a single cycle
instruction  This is to be distinguished from the situation with a
EOP which preserves the multicycle delay with A(#). This is
illustrated schematically on next page.

      It may be required to do two of some operations in one to take
advantage of the opportunity afforded by the of decoded instructions.
 Two-at-a-time EOP coupled the presence of the generalized RR
instructions will the enqueued instructions to be dequeued faster
than were enqueued.  If decoding continues at a rate, a non-delaying
queue condition arising a queue full condition means that the
enqueueing has been completely overlapped.

      As all instructions will have to EOP, and the EOP of must be in
sequence, a key aspect of improving potential for overlap is to
promote the EOP of the instruction and to uncouple the EOP from the
of all its cache access activities.  That is to that simply
reprioritizing cache accesses, which trades cycle of delayed EOP for
a cycle of access for a queued is not as effective as reordering the
EOP and accesses.

      EOP requirements are design dependent and can be as identifying
the point where a recoverable with respect to a particular
instruction has been  Even without promoting the EOP of a multicycle
it is possible to consider allowable of the fetches and stores
associated with instructions so that, without violating any
restrictions associated with conceptual order remaining within the
bounds of the available store one can EOP a multicycle instruction
before all of stores are completed in the memory.  Then, giving these
a lower priority will achieve a higher degree of with enqueued
instructions.
   The result, as illustrated above, is to allow:
   The EOP of all...