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Debug Aid for Wild Branch Conditions

IP.com Disclosure Number: IPCOM000099292D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 1 page(s) / 49K

Publishing Venue

IBM

Related People

Movall, PE: AUTHOR [+2]

Abstract

Described is a way to aid in a debug of a wild condition. It also is an aid in the use of other such as in-circuit emulators.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 67% of the total text.

Debug Aid for Wild Branch Conditions

       Described is a way to aid in a debug of a wild
condition. It also is an aid in the use of other such as in-circuit
emulators.

      A wild branch occurs when the processor jumps to an address
space and executes the data that are stored  This type of error is
usually detected when the data is fetched as an instruction, or
operation code, is an instruction.  This invalid operation code then
a processor exception and could halt the system.

      This method to debug wild branch conditions requires hardware
and software support.  The key pieces of this aid include:
   1.   A hardware feature in the processor to halt on an
        invalid
        operation  code.
   2.   A software feature to accurately log processor
        information
        before and after the processor exception.
   3.   A software feature to fill memory with an invalid
        op code.

      Typically, a processor supports the first requirement.  The
requirement is usually implemented in an system.  The third
requirement is supported by memory diagnostic code, or by operating
system code fills memory before any code is loaded.  Since the code
and diagnostic code are usually present and the support is typically
included, the only change is to the diagnostic code, which is to
change the that is left in memory when the tests are completed.

      During a wild branch condition without thi...