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Browse Prior Art Database

Improved Bit String Manipulation in RISC Processor

IP.com Disclosure Number: IPCOM000099296D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 1 page(s) / 51K

Publishing Venue

IBM

Related People

Groves, RD: AUTHOR [+2]

Abstract

This disclosure describes new instructions for processors. These bit string manipulation instructions support situations in which the beginning and end of need to be computed at run time. The RT processor only rudimentary support for bit strings while the minicomputer provided a much richer set of bit string instructions involving a rotator, mask, and unit which have been disclosed previously. Subsequent processors have followed similar approaches. The 801 definitions allowed for the rotation amount to specified at run time or compile time, but the mask could be generated at compile time. If the mask needed to be at run time, a series of several other instructions to be assembled to compute the mask.

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Improved Bit String Manipulation in RISC Processor

       This disclosure describes new instructions for processors.
 These bit string manipulation instructions support situations in
which the beginning and end of need to be computed at run time.  The
RT processor only rudimentary support for bit strings while the
minicomputer provided a much richer set of bit string instructions
involving a rotator, mask, and unit which have been disclosed
previously.  Subsequent processors have followed similar approaches.
The 801 definitions allowed for the rotation amount to specified at
run time or compile time, but the mask could be generated at compile
time.  If the mask needed to be at run time, a series of several
other instructions to be assembled to compute the mask.  In addition,
if an function was required, several more instructions were  An
example of such a case is dealing with data on mapped displays where
the bit pointers are computed at time.  Using the same essential
rotator, mask and merge two new instructions are defined.  These
instructions called Mask Generate (maskg) and Mask Insert From
(maskir).  The maskg instruction is defined with register fields.
The first field specifies the that will be updated with the generated
mask.  The field specifies a register that contains the bit to start
the mask of ones.  The third field specifies register that contains
the bit number to stop the mask of  The maskir instruction is also
defined by three fields.  Th...