Browse Prior Art Database

High Speed Buffer for N X 1 Multiplexing

IP.com Disclosure Number: IPCOM000099302D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 143K

Publishing Venue

IBM

Related People

Birman, A: AUTHOR [+4]

Abstract

This document discloses a buffer unit which stores received on a number of channels (up to 200) over a single high speed (up to 200 Mbps) Time Multiplexed (TDM) link, into logically distinct within a RAM-based storage unit. Received are read out sequentially according to a global all channels) first-come, first-served (FCFS) policy minimizes the overall storage requirement. Input and operations are performed independently. The buffer can operate with a variable number of channels on the link (e.g., two 50 Mbps channels or a hundred 1 Mbps as well as variable packet sizes. The buffer can also be used with several lower speed channels of one high speed TDM link by introducing an multiplexer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Speed Buffer for N X 1 Multiplexing

       This document discloses a buffer unit which stores
received on a number of channels (up to 200) over a single high speed
(up to 200 Mbps) Time Multiplexed (TDM) link, into logically distinct
within a RAM-based storage unit.  Received are read out sequentially
according to a global all channels) first-come, first-served (FCFS)
policy minimizes the overall storage requirement.  Input and
operations are performed independently.  The buffer can operate with
a variable number of channels on the link (e.g., two 50 Mbps channels
or a hundred 1 Mbps as well as variable packet sizes.  The buffer can
also be used with several lower speed channels of one high speed TDM
link by introducing an multiplexer.

      The buffer unit consists of storage and control  The RAM-based
storage element reconstructs and packets received over the time slots
associated with channel.  The control element consists of dedicated
that updates and stores the pointers needed to where data should be
written to and read from.  Fig. provides an overview of the structure
of the buffer unit operates synchronously.  Its operation is best by
describing the associated data and control

      At each time slot the buffer receives a byte from the channel.
The Slot Channel Map driven by the Slot Clock the corresponding
channel number.  The channel is used to access the pointer tables and
to retrieve two pointers (W-PTR and H-PTR) associated with this  The
pointer W-PTR indicates the memory location the received byte should
be written.  The byte will, only be written if it belongs to a
packet, as by the INF-I signal being active.  In case the is written,
the W-PTR is updated in the W-PTR Update to provide the value of the
new memory location where next byte from the same channel must be
written.  The Update Logic is detailed in a later paragraph.  The
W-PTR is stored back in the Write PTR Table at the associated with
its channel.  As pipelining are used to retrieve and store the
different a selector is provided to allow the immediate of the
updated W-PTR to the register.  This path used only in the case of
consecutive slots belonging to same channel, for which the updated
pointer has not yet stored back in the table.

      The H-PTR is used to remember the memory location of the stored
byte of a packet.  The H-PTR is the W-PTR of first byte of a packet
which is stored in the Head PTR when the STARTF-I signal is active.
The H-PTR is each time a byte fro...