Browse Prior Art Database

Error Prevention Mechanism for of Asynchronous Event

IP.com Disclosure Number: IPCOM000099303D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Branstad, MW: AUTHOR [+2]

Abstract

Described is a method of retrieving asynchronously data without sacrificing data integrity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Error Prevention Mechanism for of Asynchronous Event

       Described is a method of retrieving asynchronously data
without sacrificing data integrity.

      Several registers in a chip could change asynchronously the
processor register accesses.  If a processor 'Read' one of these
registers occurs as the data are changing, parity may not be at the
correct state for the data  This would indicate a false parity error.
 The in question are the timers, status, and modem

      A polarity-hold level sensitive scan design latch with clock
controls is added in front of the data driver each of the data bits
with this potential problem, as in Fig. 1.  During a processor
'Read', data from the registers are selected through the multiplexers
(MUXs)  The chip indicates to the processor that data are to be taken
by driving 'DTACK'.  At this time, the 'B' to the output latch is
turned 'OFF' to prevent any at the driver from taking place.  Data
parity is from the output of the latch. 

                            (Image Omitted)

      When the processor cycle is completed, the 'B' clock is back
on, and the output latches resume in data flush  Fig. 2 provides the
timing relationship between the interface and the output latch
clocking.