Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Digital Surface Analysis Testing

IP.com Disclosure Number: IPCOM000099309D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 4 page(s) / 138K

Publishing Venue

IBM

Related People

Anderson, PM: AUTHOR [+7]

Abstract

Disclosed is a circuit for implementing a digital analysis test (SAT). Surface analysis testing is to locate defective areas on the surface of magnetic The digital SAT technique a eliminates the need for hardware external to a direct access storage device

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Digital Surface Analysis Testing

       Disclosed is a circuit for implementing a digital analysis
test (SAT).  Surface analysis testing is to locate defective areas on
the surface of magnetic  The digital SAT technique  a eliminates the
need for hardware external to a direct access storage device

      Digital SAT is accomplished through the use of digital
processing logic.  This logic is included with other used to
implement the DASD data channel function. SAT uses a sampled version
of the analog readback as input and generates a logic signal output
which the occurrence of a defect.  The detection of the testing
algorithm is adjustable by a clip level parameter.  Both increasing
and signal amplitudes is detected by the algorithm.  The also allows
for "SELF-SAT" capability, where DASD device performs surface
analysis testing on itself aid from any external equipment.

      The digital SAT technique is closely coupled with the data
channel.  The data channel produces 6-bit digital by use of an A/D
converter.  These samples represent amplitude of the analog readback
signal at discrete in time.  The SAT circuitry uses these already
samples as input.  A data pattern is intended to be used with SAT.
The pattern is the same as the sector field: a repeating <+1, +1, -1,
-1> trinary  Sync pattern is ideal for SAT since it appears when read
back and is not affected by channel tolerances.  The A/D scale and
ideal trinary levels are illustrated by Fig. 1.

...