Browse Prior Art Database

Reliable Butted Emitter NPN Channel Stop Transistor

IP.com Disclosure Number: IPCOM000099312D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Hook, TB: AUTHOR

Abstract

This design and process for making a butted emitter sidewall channel stop (SCST) results in higher reliability than is in previous NPN SCSTs.

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Reliable Butted Emitter NPN Channel Stop Transistor

       This design and process for making a butted emitter
sidewall channel stop (SCST) results in higher reliability than is in
previous NPN SCSTs.

      Fig. 1 is a plan view, Fig. 2 is a cross section through of
Fig. 1, and Fig. 3 is a cross section through B-B of Fig.1 a standard
SCST construction.   Referring first to Fig. a highly doped N
subcollector layer 10 is formed on a doped P substrate 12.  A lightly
doped N collector 14 is deposited.  Masking and heavy Ndoping is used
to the reachthrough region 16 shown in Fig. 2.  Another and P doping
operation forms base region 18. 20 is then defined and doped N+.
Trench 22 is then through all layers, as shown in Fig. 2 and Fig. 3.
1 shows hatched reachthrough connection region 24, base region 26,
and emitter connection region 28.

      Fig. 4 is a B-B cross section after adding insulator 30, an
opening and performing a non-standard gaseous of a P type dopant to a
level insufficient to any of the N+ regions 10, 20, or 16.  Standard
is resumed by forming an insulating layer (not on trench sidewalls
and on the device surface. are etched through the insulator for
device  Trench 22 is filled with an insulator, and metal connections
to device terminals are made as usual.

      Devices made by this process are stable under forward and are
otherwise comparable with devices made the P type sidewall diffusion.