Browse Prior Art Database

Lockbit Detection Using a and a Comparator

IP.com Disclosure Number: IPCOM000099314D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Bakoglu, HB: AUTHOR [+2]

Abstract

A new hardware implementation of a data locking is described in which the polarity of a lockbit is by an address decoder and a precharged This technique offers a faster and denser to a 32-to-1 multiplexer that would otherwise be to select one out of 32 lockbits.

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This is the abbreviated version, containing approximately 58% of the total text.

Lockbit Detection Using a and a Comparator

       A new hardware implementation of a data locking is
described in which the polarity of a lockbit is by an address decoder
and a precharged  This technique offers a faster and denser to a
32-to-1 multiplexer that would otherwise be to select one out of 32
lockbits.

      In an architecture with data locking, a 4k-byte page can
divided into 32 lines of 128 bytes.  Data locking generates an
interrupt at the first reference of a to a new line.  The operating
system uses these to maintain lock and journaling functions.

      A 4k-byte page is divided into 32 128-bit lines and 'j'
corresponds to line 'j'.  Accordingly, bits 20 24 of a 32-bit address
determine the line number 'j'. locking condition depends on the
polarity of lockbit  In this implementation, 32 lockbits are stored
in a Look-a-side Buffer (TLB).  As shown in Fig. 1, 20 to 24 of the
address are decoded to 32 bits and are to a precharged comparator
with the complement of the from the TLB (the TLB array provides both
true and out  If the output of the comparator is a 1, the lockbit a
1; otherwise, it is a 0.  A precharged comparator is in Fig. 2.  The
output is precharged high, and it will discharged only if both inputs
in one of the legs are  This is faster and more area efficient than
using a decoder and a 32-to-1 multiplexer in front of the to select
the lockbit 'j'.  In this new method, bits 20 24 of the address are
decoded in parallel with...