Browse Prior Art Database

Elimination of a Critical Layout in CMOS Technology

IP.com Disclosure Number: IPCOM000099318D
Original Publication Date: 1990-Jan-01
Included in the Prior Art Database: 2005-Mar-14
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Chailloux, D: AUTHOR [+5]

Abstract

Disclosed below is an improved layout that avoids potential resistive metal open in current CMOS

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This is the abbreviated version, containing approximately 100% of the total text.

Elimination of a Critical Layout in CMOS Technology

       Disclosed below is an improved layout that avoids
potential resistive metal open in current CMOS

      Fig. 1A shows a typical topology that is used to make through
via-holes. Fig. 1B shows a view of the topology.  P1 stands for poly
M1 for metal level, CA for contact via-hole, Ti for and SG for
silicon glass.

      The M1 pitch and the M1 to CA space are at minimum  The
critical area is represented by the zone (Fig. 1A).

      Fig. 1B makes clear the existence of a highly resistive because
only the Ti layer exists in the via-hole.

      The contact opening, because of process tolerances, does occur
at the minimum SG thickness; the left edge of the will thus be higher
and sharper than the right edge.  The layer may be evaporated in a
discontinuous manner such an edge, leading to the risk of resistive
metal mentioned above.  An solution to this problem would be to relax
groundrules of the M1 to CA space, but this would affect the circuit
density.

      Since the problem only occurs in the above-described it is
easier to change the configuration by either down the CA opening or
moving up the M1 metal land, solutions being shown in Fig. 2.